Field of the Invention
This technology relates to page buffer output, and more particularly relates to counting errors in page buffer output.
Description of Related Art
As technology shrinks, the random defects of memory cells increase, for example, open bit-line contacts in a NAND Flash array. This kind of defect can be either repaired with redundant cells, or tolerated if the number of defects is limited during a program or erase operation. If tolerated, the total number of defects for both erase and program operations in one page should be less than the ECC number requirement for each page, so that the ECC in read operation can fix the errors from the defects. If tolerated, also the page buffer counts the number of the error bits during program and erase verify operations.
FIG. 1 is a simplified circuit diagram of a circuit that measures a number of errors in page buffer output. The circuit of FIG. 1 is fast but not accurate, as follows.
The page buffer output status latches 12, 14, 16, 18, 20, and 22 indicate whether a corresponding page buffer output status bit has a bit status. In one example, the bit status indicates an error status of a corresponding bit line, such as one of at least pass and fail. The page buffer output status latches 12 and 22 have the failed bit status, and output the high value. The page buffer output status latches 14, 16, 18, and 20 have a pass bit status, and output the low value. The value of the page buffer output status latches is coupled to a corresponding Fail Bit Detection Unit (FBDU).
FBDU circuits 24, 26, 28, 30, 32, and 34 are coupled to a corresponding one of the page buffer output status latches 12, 14, 16, 18, 20, and 22. An FBDU includes two serially connected NMOS transistors. In each FBDU, one of the two serially connected NMOS transistors has a gate coupled to signal VNC 36 which enables all of the FBDU circuits 24, 26, 28, 30, 32, and 34. In each FBDU, the other one of the two serially connected NMOS transistors has a gate coupled to a corresponding one of the page buffer output status latches 12, 14, 16, 18, 20, and 22; this serially connected NMOS transistor is turned on when the corresponding one of the page buffer output status latches has a failed bit status, and turned off otherwise. Transistors other than MOS may be used.
Supply voltage VDD 40 provides current of (N+½)*I through PMOS VPC 38, where N is the maximum number of failed bits that can be indicated by the page buffer output status latches; in some cases N can be the maximum number of error bits which can be repaired via error correction. For each page buffer output status latch with a bit status failure, the corresponding FBDU sinks “I” current. K failures in the page buffer output status latches sink a total current of K*I. The difference between the supplied and sunk currents is (N−K+½)*I, which flows into the DET input terminal of the NAND gate 42.
NAND gate 42 also has another, EN input and an output coupled to latch 44, which in turn has an output of PASS or FAIL.
The output is as follows:                K<(N+½)→Pass        K>(N+½)→Fail        
The circuit of FIG. 1 is fast, because of simultaneous detection of all page buffer output status latches of the page buffer. Disadvantage of the circuit of FIG. 1 include:
i) The sunk current is from a current mirror.
ii) Mismatches among the transistors impact the current accuracy.
iii) When N is large, there is a small difference in the input currents at the DET input terminal between a PASS result and a FAIL result, which impacts the detection accuracy.
FIG. 2 is a simplified circuit diagram of a circuit that detects the position of an error in page buffer output through binary search. The circuit of FIG. 2 is accurate but not fast, as follows.
Each page buffer output status latch is coupled to a corresponding instance of the “FBDU” circuit of FIG. 2 including a latch 48, which can be individually selected via SELECT signal 52, individually reset via the RESET signal 50, and loaded via LOAD signal 46. All of the “FBDU” circuits are coupled to the same DET output 54.
Signal SELECT 52 is the decoded address signal. If the address is selected, the SELECT value is “H”; and if the address is not selected, the SELECT value is “L”.
In the first step, the LOAD signal value is “H” and the failure status information is loaded from the corresponding page buffer output status bit to the latch 48.
The second step begins the process of detecting the failure status bit. First all addresses are selected, such that any failure status bit pulls down the DET signal 54 to 0. If the DET signal 54≠1, then at least one failure status bit exists. Then in a binary search, the failure address is located. Then the bit status of the located FBDU is reset, and the failure count is incremented.
Finally, the second step is repeated, until no failure is found when all addresses are selected, such that the DET signal 54=1.
Because the circuit of FIG. 2 counts failure status bits on a digital logic-like basis, the circuit of FIG. 2 is very accurate. However, for N address bits (representing 2N addresses), each failure status bit requires checking the logic N+1 times for each failure due to the binary search for each failure status bit. Such a repeated search is time consuming.
FIG. 3 is a schematic of different steps in a process of detecting the position of an error in page buffer output through binary search, showing the contents of the memory elements in the multiple stages of the circuit series that counts the number of errors in page buffer output, and the output value of the last stage of the circuit series.
A different FBDU with its own latch is represented by each of the columns 56, 58, 60, 62, 64, 66, 68, and 70. The latches are initialized by corresponding page buffer output status bits. The first row 72 shows that the FBDUs of columns 56 and 66 are initialized to a failure status, and that the rest of the FBDUs are not.
Rows 74, 76, 78, and 80 are steps in a binary search for the first FBDU with a latch initialized to a failure status. In each case, the DET signal=0, so a failure bit is located among the selected FBDUs. In row 82, after a failure bit has been localized to the FBDU of column 56, the latch of FBDU of column 56 undergoes a RESET signal. In future searches, the FBDU of column 56 will not cause the DET signal to fall to 0, and the total of failure bits is incremented by 1.
The binary search process for FBDUs with a latch holding the failure status bit continues, because the prior search iteration concluded with DET=0. Row 82 shows that the FBDU of column 66 holds a failure status, and that the rest of the FBDUs are not.
Rows 86, 88, 90, and 92 are steps in a binary search for the next FBDU with a latch holding a failure status. In rows 86 and 90, the DET signal=0, so a failure bit is located among the selected FBDUs. In rows 88 and 92, the DET signal=1, so a failure bit is not located among the selected FBDUs, indicating that the FBDU with the latch holding the failure status was among the unselected FBDUs. In row 94, after a failure bit has been localized to the FBDU of column 66, the latch of FBDU of column 66 undergoes a RESET signal. In future searches, the FBDU of column 66 will not cause the DET signal to fall to 0, and the total of failure bits is incremented by 1.
In row 98, the final iteration begins again with all FBDUs selected. Because DET=1, none of the FBDUs includes a latch holding a failure status. The total of failure bits is not incremented anymore, and holds the final total of FBDUs with a latch initialized to a failure status.
The circuit of FIG. 2 following the process of FIG. 3 is slow but accurate.
It would be desirable to measures a number of errors in page buffer output both quickly and accurately.